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Heterogeneous System Architecture (HSA) is a computer processor architecture that integrates central processing units and graphics processors on the same bus, with shared memory and tasks. The HSA is being developed by the HSA Foundation, which includes (among many others) AMD and ARM. The platform's stated aim is to reduce communication latency between CPUs, GPUs and other compute devices, and make these various devices more compatible from a programmer's perspective,〔(【引用サイトリンク】url=http://developer.amd.com/resources/heterogeneous-computing/what-is-heterogeneous-system-architecture-hsa/ )〕 relieving the programmer of the task of planning the moving of data between devices' disjoint memories (as must currently be done with OpenCL or CUDA). Cuda and OpenCL as well as most other fairly advanced programming languages can use HSA to increase their execution performance.〔(【引用サイトリンク】title=LCE13: Heterogeneous System Architecture (HSA) on ARM )〕 Heterogeneous computing is widely used in system-on-chip devices, such as tablets, smartphones, and other mobile devices. HSA allows programs to use the graphics processor for floating point calculations without separate memory or scheduling.〔(【引用サイトリンク】website=Embedded Computing Design )〕 == Overview == Originally introduced by the Cell Broadband Engine, sharing system memory directly between multiple system actors makes heterogeneous computing more mainstream. Heterogeneous computing itself refers to systems that contain multiple processing units central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), or any type of application-specific integrated circuits (ASICs). The system architecture allows any accelerator, for instance a graphics processor, to operate at the same processing level as the system's CPU. Among its main features, HSA defines a unified virtual address space space for compute devices: where GPUs traditionally have their own memory, separate from the main (CPU) memory, HSA requires these devices to share page tables so that devices can exchange data by sharing pointers. This is to be supported by custom memory management units.〔 To render interoperability possible and also to ease various aspects of programming, HSA is intended to be ISA-agnostic for both CPUs and accelerators, and to support high-level programming languages. So far, the HSA specifications cover: * HSA Intermediate Layer (HSAIL), a virtual instruction set for parallel programs * * similar to LLVM Intermediate Representation and SPIR (used by OpenCL and Vulkan) * * finalized to a specific instruction set by a JIT compiler * * make late decisions on which core(s) should run a task * * explicitly parallel * * supports exceptions, virtual functions and other high-level features * * syscall methods (I/O, printf, etc.) * * debugging support * HSA memory model * * compatible with C++11, OpenCL, Java and .NET memory models * * relaxed consistency * * designed to support both managed languages (e.g. Java) and unmanaged languages (e.g. C) * * will make it much easier to develop 3rd-party compilers for a wide range of heterogeneous products programmed in Fortran, C++, C++ AMP, Java, et al. * HSA dispatcher and run-time * * designed to enable heterogeneous task queueing: a work queue per core, distribution of work into queues, load balancing by work stealing * * any core can schedule work for any other, including itself * * significant reduction of overhead of scheduling work for a core Mobile devices are one of the HSA's application areas, in which it yields improved power efficiency.〔 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Heterogeneous System Architecture」の詳細全文を読む スポンサード リンク
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